Embodiments of this disclosure relate to a probe device for electrical testing an integrated circuit device and probe card using the same, and more particularly to a probe device for electrical testing an integrated circuit device and probe card capable of adjusting the probe pressure applied on an integrated circuit device under test by the probe and aligning the probe along the center line automatically.
Generally, it is necessary to test the electrical characteristic of integrated circuit devices on the wafer level for checking whether the integrated circuit device satisfies the product specification. Integrated circuit device with electrical characteristic satisfying the specification will be selected to carry on the subsequent packaging process, and the other devices will be discarded to avoid additional packaging cost. Another electrical property test will be performed on the integrated circuit device after the packaging process is completed to sieve out the disqualified devices to increase the product yield.
There are two major types of probes according to the prior art, i.e., the cantilever probe and the vertical probe. The cantilever probe provides appropriate vertical displacement when the probe tip contacts an integrated circuit device under test via a cantilever contact structure to prevent the integrated circuit device under test from excessive probe pressure applied by the probe tip. However, the cantilever contact structure occupies a larger planar space in a matrix array probing, which constrains the cantilever probe to be arranged in a fine pitch manner corresponding to the integrated circuit device under test with the high density of pin, therefore it cannot be applied to the testing of the integrated circuit device with high density of pin.
The vertical probe offers the vertical displacement required by the probe tip to contact the integrated circuit device under test using the deformation of the probe body itself, and can be arranged in a fine pitch manner corresponding to the integrated circuit devices under test with high density of pin. However, if the deformation of the probe body is so large, adjacent probes may contact each other and causes short circuit or collision.
U.S. Pat. No. 5,914,613 discloses an elastic membrane testing module for testing electrical characteristic of the integrated circuit device. The elastic membrane testing module includes several probes positioned on an elastomeric layer, and provides all probes a proper vertical moving displacement via the elastomeric layer to adjust a probe pressure, which is enough to scrape an oxide layer on the pad as each probe contacts the pad of the integrated circuit device under test. However, the moving displacement provided by the elastomeric layer cannot be self adjustable individually for each probe to conform with the irregularities of testing pads or bumps, and thus cause the moving displacements are different from one to another; the moving displacement is larger at the center of the elastomeric layer and relatively smaller around the peripheral of the integrated circuit device. Consequently, the probe at the center may apply an excessive probe pressure to damage the pad, while the probe around the peripheral may not be enough to scrape the oxide layer on the pad. That is, the probes cannot scrape the oxide layer on the pad evenly and the impedances are different. Additionally, since the elastomeric layer is a multi-layer structure and consists of several materials, the thermal expansion coefficient difference between different materials limits application of the elastic membrane testing module in high temperature electrical property measurement.